1. Technical Field of the Invention
The present invention relates to a power-on reset circuit and, in particular, to the implementation of a power-on reset circuit with a glitch sensing capability in a single chip or multi-chip electronic system environment.
2. Description of Related Art
A power-on reset circuit is included in many electronic devices and, in particular, those electronic devices which include microprocessing or other digital integrated (logic) circuit elements. It is desirable to initialize or reset these types of elements to a particular known logical state every time power is initially applied. The power-on reset circuit typically operates to detect a powering-up of the electronic device, and in response thereto inhibits activation of the electronic device (or, perhaps, certain specific elements thereof) for a period of time believed sufficient for full and stabilized power to become available for device use. A reset of the electronic device (or its included elements) to a known state is then initiated.
It is desirable for the power-on reset circuit to be activated not only when power is first applied to the electronic device, but also in instances where a glitch in the applied power occurs. What is needed then is a power-on reset circuit with glitch sensing capability.
In the typical electronic device, the power-on reset circuit is implemented as a separate collection of interconnected circuit elements and/or devices. The circuit generates an output reset signal that is connected to various other elements of the electronic device which are sensitive to power variations like that experienced at first power application. This architecture is commonly utilized in multi-chip electronic systems where the power-on reset circuit is implemented in its own chip package (or perhaps as discrete components) and assembled and interconnected with other chips for the system. One disadvantage of this common architectural implementation is that the power-on reset circuit occupies valuable circuit board space that could more advantageously be utilized for the installation of other chips.
It is known to form the power-on reset circuit as a part of the same monolithic semiconductor integrated circuit chip which contains other functionalities such as logic or memory circuits. However, it is redundant and wasteful to incorporate the power-on reset circuit within each individual chip of a multi-chip electronic system. What is needed then is a mechanism to more efficiently utilize an integrated (i.e., same chip) power-on reset circuit in a multi-chip environment. Such an implementation should further support those designs wherein the multi-chip electronic system is implemented into a single integrated circuit chip.